cpu-architecture Examples and Free Source Code

Why is conditional processing of a sorted array faster than of an unsorted array?...

java c++performance cpu-architecture branch-prediction

x86_64 assembly - loop conditions and out of order execution (macro-fusion with JCC)...

loops assembly x86-64 cpu-architecture micro-optimization

Is cache coherency only an issue when storing and not when loading?...

caching concurrency x86 cpu-architecture compare-and-swap

When to use forwarding and when to use stalls to handle data hazards in pipelining (RISC V architect...

assembly cpu-architecture riscv pipelining

Is there any architecture that uses the same register space for scalar integer and floating point op...

floating-point cpu-architecture cpu-registers

How do cache lines work?...

caching memory cpu-architecture cpu-cache processor

Latency of assembly memory ops in modern CPUs...

performance assembly x86 cpu-architecture micro-optimization

Memory barriers in virtual environments - do they interrupt other cores?...

c++performance cpu-architecture atomic memory-barriers

How is load->store reordering possible with in-order commit?...

arm cpu-architecture memory-barriers

Is assembly code and machine code part of the architecture?...

assembly cpu-architecture machine-code instruction-set micro-architecture

Do assembly instructions map 1-1 to machine language?...

assembly cpu-architecture machine-code

Aligning to cache line and knowing the cache line size...

c linux caching cpu-architecture memory-alignment

Can the hardware reorder an atomic load followed by an atomic store, if the store is conditional on ...

c++multithreading cpu-architecture atomic memory-barriers

Why doesn't a Wallace tree produce numbers with more than 2n final product bits?...

algorithm cpu-architecture multiplication sat digital-logic

Write back vs Write through bandwidth...

caching cpu-architecture cpu-cache

How does the LDA instruction interact with RAM and IR on MU1 architecture?...

assembly architecture cpu-architecture

descriptor concept in NIC...

driver cpu-architecture nic

How to judge if a given workload is hyper-thread friendly?...

performance cpu-architecture hyperthreading

Atomicity of loads and stores on x86...

c++x86 cpu-architecture atomic memory-barriers

What is the stack engine in the Sandy Bridge microarchitecture?...

assembly x86 intel cpu-architecture

"docker: no matching manifest for linux/amd64 in the manifest list entries"...

docker cpu-architecture

Can I disable/turn off general protection exception when an address is not in canonical form?...

pointers assembly x86-64 cpu-architecture canonical-form

Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?...

performance x86 cpu-architecture benchmarking memory-bandwidth

What is a cache hit and a cache miss? Why would context-switching cause cache miss?...

concurrency cpu cpu-architecture cpu-cache context-switch

uops for integer DIV instruction...

assembly x86 x86-64 cpu-architecture micro-architecture

How are MMIO requests routed in CPU microarchitecture — cache-bypass on same path or a separate bus/...

cpu-architecture gem5 nic micro-architecture memory-mapped-io

What is the difference between x86 assembly and other versions of assembly?...

assembly x86 arm cpu-architecture instruction-set

What are all the different types of parallelism?...

multithreading parallel-processing cpu-architecture multicore hyperthreading

How to check CPU name, model, speed on Windows/Linux C?...

c linux cpu cpu-architecture cpu-speed

Why are all IMUL µOPs dispatched to Port 1 only (on Haswell), even when multiple IMULs are exec...

assembly x86-64 cpu cpu-architecture intel