cpu-architecture Examples and Free Source Code

How to get whether the OS is 32-bit or 64-bit by UNIX command or in C?...

unix operating-system command cpu-architecture 32bit-64bit

Itanium seq_cst Fence and Relaxed Atomics Not Using Plain Loads and Stores...

c++cpu-architecture atomic memory-barriers itanium

Why didn't the x86-32 architecture get more general purpose registers before x86-64?...

x86 x86-64 cpu-architecture cpu-registers

In C++ atomic operations, are the generated values allowed to circularly depend on their own computa...

c++multithreading cpu-architecture atomic arm64

Descriptor concept in NIC...

driver cpu-architecture nic

What is the latency of `clwb` and `ntstore` on Intel's Optane Persistent Memory?...

x86-64 intel cpu-architecture persistent-memory

How to force cpu core to flush store buffer in c?...

c multithreading x86 cpu-architecture cpu-cache

In C++ atomic operations, are the generated values allowed to circularly depend on their own computa...

c++multithreading cpu-architecture atomic arm64

Instruction fetch stage...

assembly computer-science cpu-architecture

Cost of cache miss and the number of memory round trips...

caching cpu-architecture cpu-cache

Why is conditional processing of a sorted array faster than of an unsorted array?...

java c++performance cpu-architecture branch-prediction

x86_64 assembly - loop conditions and out of order execution (macro-fusion with JCC)...

loops assembly x86-64 cpu-architecture micro-optimization

Is cache coherency only an issue when storing and not when loading?...

caching concurrency x86 cpu-architecture compare-and-swap

When to use forwarding and when to use stalls to handle data hazards in pipelining (RISC V architect...

assembly cpu-architecture riscv pipelining

Is there any architecture that uses the same register space for scalar integer and floating point op...

floating-point cpu-architecture cpu-registers

How do cache lines work?...

caching memory cpu-architecture cpu-cache processor

Latency of assembly memory ops in modern CPUs...

performance assembly x86 cpu-architecture micro-optimization

Memory barriers in virtual environments - do they interrupt other cores?...

c++performance cpu-architecture atomic memory-barriers

How is load->store reordering possible with in-order commit?...

arm cpu-architecture memory-barriers

Is assembly code and machine code part of the architecture?...

assembly cpu-architecture machine-code instruction-set micro-architecture

Do assembly instructions map 1-1 to machine language?...

assembly cpu-architecture machine-code

Aligning to cache line and knowing the cache line size...

c linux caching cpu-architecture memory-alignment

Can the hardware reorder an atomic load followed by an atomic store, if the store is conditional on ...

c++multithreading cpu-architecture atomic memory-barriers

Why doesn't a Wallace tree produce numbers with more than 2n final product bits?...

algorithm cpu-architecture multiplication sat digital-logic

Write back vs Write through bandwidth...

caching cpu-architecture cpu-cache

How does the LDA instruction interact with RAM and IR on MU1 architecture?...

assembly architecture cpu-architecture

How to judge if a given workload is hyper-thread friendly?...

performance cpu-architecture hyperthreading

Atomicity of loads and stores on x86...

c++x86 cpu-architecture atomic memory-barriers

What is the stack engine in the Sandy Bridge microarchitecture?...

assembly x86 intel cpu-architecture

"docker: no matching manifest for linux/amd64 in the manifest list entries"...

docker cpu-architecture