riscv Examples and Free Source Code

Can (and should) a page table entry contain its own lock on RISC-V in Rust?...

rust synchronization atomic riscv paging

Why do dynamic value prints panic in my no_std kernel?...

string rust kernel riscv

In the RISC V Assembler, what does the ".weak" assembler directive do?...

assembly riscv gnu-assembler mpu

Risc-v compressed instruction alignment...

assembly caching riscv memory-alignment

RISC-V difference between jal and jalr...

assembly function-pointers riscv

Do RISC-V kernel-space calling conventions exist?...

assembly linux-kernel system-calls riscv calling-convention

RISC-V GCC Force Linker Relaxation with GP Register to Address Static Data...

gcc linker riscv

LLVM generates stack usage on simple RISC-V function where GCC doesn't...

c++llvm riscv

Risc-V atomic instructions...

assembly atomic riscv

How to make a simple Multi Core multithreaded baremetal program?...

c operating-system scheduled-tasks posix riscv

RISC-V Interrupt Handling Flow...

assembly interrupt riscv irq

What Store/Store reordering do modern CPUs do in practice?...

arm64 riscv memory-barriers memory-model

GNU as recursive/loop macro expected output...

assembly macros riscv gnu-assembler

Context switch in interrupt routine...

assembly riscv context-switch

3D Morton code computation utilizing carry-less multiplication...

algorithm assembly bit-manipulation riscv micro-optimization

How do machine read the instructions of Risc-v...

riscv opcode

Why __sync_or_and_fetch builtin in a loop renders as an endless loop with -O2 and -O3?...

c gcc atomic riscv spinlock

How are interrupts handled when interrupts are disabled?...

riscv

RISC-V U-Format instruction immediate confusion...

assembly riscv machine-code immediate-operand instruction-encoding

Why is RISC-V GCC uselessly reserving stack space in a function that returns a small struct?...

assembly gcc optimization riscv

GCC Linker error relocation error in RISCV 64 bit...

linker riscv

Why aren’t opcode and funct7 and funct3 a single 17-bit field?...

riscv

How to fix "unsafe attribute used without unsafe" in custom attribute macro?...

rust riscv

Is mulw faster than mul on riscv 64-bit platforms?...

compiler-optimization riscv

RISCV sleep (wfi) and interrupts...

embedded real-time riscv

Chisel Passing Enum type as IO...

scala riscv chisel

RISCV assembly 32bit multiplication without MUL giving incorrect result...

multiplication riscv

raise Store/AMO page fault when trying write stack in xv6's trampoline...

linux kernel riscv xv6

Discrepancy of `unsigned long` size between llvm and gcc in riscv32...

c gcc riscv clangd riscv32

Why is JALR used instead of JAL for returning from subroutines...

assembly riscv