cpu-architecture Examples and Free Source Code

Can I disable/turn off general protection exception when an address is not in canonical form?...

pointers assembly x86-64 cpu-architecture canonical-form

Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?...

performance x86 cpu-architecture benchmarking memory-bandwidth

What is a cache hit and a cache miss? Why would context-switching cause cache miss?...

concurrency cpu cpu-architecture cpu-cache context-switch

uops for integer DIV instruction...

assembly x86 x86-64 cpu-architecture micro-architecture

How are MMIO requests routed in CPU microarchitecture — cache-bypass on same path or a separate bus/...

cpu-architecture gem5 nic micro-architecture memory-mapped-io

What is the difference between x86 assembly and other versions of assembly?...

assembly x86 arm cpu-architecture instruction-set

What are all the different types of parallelism?...

multithreading parallel-processing cpu-architecture multicore hyperthreading

How to check CPU name, model, speed on Windows/Linux C?...

c linux cpu cpu-architecture cpu-speed

Why are all IMUL µOPs dispatched to Port 1 only (on Haswell), even when multiple IMULs are exec...

assembly x86-64 cpu cpu-architecture intel

basic operations cpu time cost...

optimization cpu-architecture

Is CPU multithreading effected by divergence?...

multithreading parallel-processing gpu cpu cpu-architecture

Why is rep movsb slow for overlapping forward memmove, and why does libc use it?...

c++performance x86 cpu-architecture memmove

Micro fusion and addressing modes...

assembly x86 intel cpu-architecture iaca

What is instruction fusion in contemporary x86 processors?...

assembly x86 cpu-architecture

CLDEMOTE support in intel CPUs...

x86 cpu-architecture intel cpu-cache instruction-set

How is a 15-byte instruction transferred from memory to CPU?...

assembly x86-64 cpu-architecture cpu-registers instruction-set

Why is memory aliasing needed?...

arm stm32 cpu-architecture processor stm32f4

Which resources of a modern x86 CPU core are occupied by memory transactions in flight?...

memory x86 cpu-architecture memory-bandwidth

How to support Carryless Multiplication operation in .NET 8.0 on various platforms...

c#assembly cpu-architecture .net-8.0 crc

Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths...

performance assembly x86 cpu-architecture perf

Purpose of the .bin directory within node_modules? What are binaries?...

node.js npm node-modules cpu-architecture

What is the overhead of jumps and call-rets for CPU front-end decoder?...

performance assembly x86 cpu-architecture branch-prediction

Can atomic operations of different sizes be mixed?...

c cpu-architecture atomic hardware

Why is the size of L1 cache smaller than that of the L2 cache in most of the processors?...

caching memory cpu-architecture processor cpu-cache

Why CPU speculative execution does not cause OOB program crash?...

security memory cpu cpu-architecture speculative-execution

Can branch prediction cause illegal instruction?...

assembly x86-64 cpu-architecture branch-prediction speculative-execution

difference between speculation and prediction...

cpu-architecture branch-prediction speculative-execution

What do x86_64, i386, ia64 and other such jargons stand for?...

x86-64 processor cpu-architecture instruction-set itanium

Python: get windows OS version and architecture...

python windows cpu-architecture

minimum required atomic instructions to support C++11 concurrency libraries...

c++c++11 assembly cpu-architecture atomic