quartus Examples and Free Source Code

Binary value representation issue in verilog...

verilog quartus

Compile error that shows 'instance is undefined entity "(symbol name)"...

compiler-errors quartus

In Verilog, I'm trying to use $readmemb to read .txt file but it only loads xxxxx (don't car...

memory verilog quartus test-bench

Verilog full adder...

verilog system-verilog fpga hdl quartus

How to Fix “Net Cannot Be Assigned More Than One Value” Error When Using Multiple SPI Modules?...

verilog system-verilog spi quartus

Correct syntax of SystemVerilog $display to produce formatted messages in Quartus message window...

system-verilog quartus

Error (10170): HDL syntax errors in Quartus (HDL)...

verilog system-verilog hdl quartus

Array of wire OR-reduction is wrong...

verilog system-verilog quartus

Modules compiling to 0 gates...

module verilog quartus

Why is "Set as Top-Level Entity" grayed out in quartus?...

verilog system-verilog hdl quartus

Verilog module always going to default case when assigning value to input...

verilog fpga quartus intel-fpga questasim

Quartus-FPGA: Disable Path Optimization...

verilog fpga quartus intel-fpga

Quartus isn't displaying Correctly...

quartus

Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand...

verilog quartus intel-fpga

Compilation error in Quartus for Verilog language...

verilog system-verilog quartus

Analyzing synchronizer MTBF in Quartus...

verilog fpga quartus intel-fpga

Why is Modelsim displaying "Error: MIF contains illegal character" when I try to simulate?...

simulation modelsim quartus

always_comb construct does not infer purely combinational logic...

compilation verilog system-verilog quartus

How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 runn...

ubuntu quartus intel-fpga

Control signal with two buttons...

vhdl quartus

When I simulate my counter in Modelsim, the outputs are undefined...

verilog modelsim quartus

Using a macro gives errors, but putting macro text in explicitly does work...

verilog system-verilog quartus

libpng12.so.0: cannot open shared object file: wrong ELF class: ELFCLASS64...

linux docker shared-libraries quartus

7-segment display with hex output...

verilog quartus

Declaration error at define_state.h: identifier is already declared in the present scope...

verilog quartus

Attempting to make a signal high for 5 clock cycles and then remain low...

verilog system-verilog quartus

The RTL viewer in Quartus is omitting redundant gates...

verilog quartus register-transfer-level

Reset a simple counter...

verilog quartus test-bench

Why is there a difference in output when using Event Control Statement and Delay statement for a sim...

verilog simulation fpga system-verilog quartus

VHDL Error(10482) object std_logic_vector is used but not declared...

compiler-errors vhdl quartus