quartus Examples and Free Source Code

On left-hand side of assignment must have a variable data type...

verilog variable-assignment system-verilog quartus synthesis

$readmemh syntax error for .mif file in Verilog HDL Intel Quartus Prime...

verilog system-verilog quartus

Verilog issue with case/always statement...

verilog quartus

Why is my 8-bit counter stuck at 0 or 255?...

verilog counter quartus 8-bit cyclone

Fatal: (vsim-3807) Types do not match between component and entity for port "out1" Without...

vhdl quartus

How do I concatenate parameters and integers?...

verilog system-verilog quartus intel-fpga

Output 'X' instead of '1' or '0' in VHDL...

vhdl quartus intel-fpga

"Serial Loader Device is missing" during Convert Programming File with Quartus Prime...

intel fpga quartus intel-fpga

ModelSim Simulation Stops Earlier than Expected...

verilog hdl modelsim quartus

How to connect module to module in Verilog?...

verilog system-verilog fpga quartus intel-fpga

How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus...

verilog system-verilog timing quartus intel-fpga

Verilog - output exuals to XXXXXXXX...

verilog fpga quartus intel-fpga

How to make a constant binary number adapt to a Generic statement in VHDL...

vhdl quartus

ModelSim-Altera error...

linux licensing modelsim intel-fpga quartus

How can I prevent that DSP blocks are synthesized away if they are not connected to a top level outp...

verilog fpga quartus intel-fpga

How do I load an FPGA's Registers with Data?...

verilog quartus intel-fpga

How can I stop quartus from jumping to the 'compilation report'?...

quartus

Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined...

vhdl intel-fpga quartus

How to drive outputs in Verilog...

verilog fpga i2c quartus

How to get rid of truncate warnings when initializing a parameter-sized array?...

verilog system-verilog quartus

Type of identifier does not agree with its usage as "boolean" type - VHDL in Quartus...

vhdl fpga identifier hdl quartus

I wrote this code in Verilog and there are no error messages, but it doesn't work...

verilog system-verilog hdl modelsim quartus

Swapping 2 parameters in always_ff @...

verilog system-verilog quartus

VHDL count and shift...

vhdl quartus

How do I make Quartus II compile faster...

vhdl quartus

Changing triggering edge depending on clock polarity signal...

vhdl clock edges quartus

Verilog HDL syntax error at practice.v(7) near text "or"; expecting ")"...

syntax-error verilog quartus

Capturing the right posedge clock in Quartus waveform...

verilog quartus test-bench digital-logic register-transfer-level

The clock speed is two times faster when the clock duty cycle is 50%...

vhdl verilog fpga quartus intel-fpga

Unknown values (X) in simulation of parking lot gate...

vhdl simulation quartus