Is the Intel Xeon Phi usable without a costly Intel Compiler?...

Assembly syntax for masked vector Intel AVX-512 instructions...

Required time to offload a function to Intel Xeon Phi...

ICC compiler - error: parallel loop condition does not test loop control variable...

Translating Intel's #pragma offload to OpenMP for Xeon Phi (performance issues and other questio...

Fast popcount on Intel Xeon Phi...

How do the Conflict Detection instructions make it easier to vectorize loops?...

How to bind my job to intel xeon phi coprocessor?...

What it takes to make OpenACC/OpenMP4.0 offloading to nvidia/mic work om GCC?...

Are there SIMD(SSE / AVX) instructions in the x86-compatible accelerators Intel Xeon Phi?...

Intel MIC - sum of intrinsic vector elements...

Intel Xeon Phi offload code + STL vector...

changing thread number doesn't affect code...

Offload daemon on xeon phi 5110p...

Segmentation fault due to data alignment issue on MIC...

Is there a simulator/emulator of Xeon Phi?...

Streaming Stores Segmentation Fault on Intel MIC...

How to profile for cache performance of an application that runs natively on Intel MIC architecture...

How to differentiate between Intel Xeon Phi Coprocessors 7120P, 7120X, 7120D, 7120A...

How can we know whether Intel Xeon Phi coprocessor is present or not...

Intel C++ compiler gives "offload constructs are not supported on this platform" error...

Can't force inlining C++ function using Intel compiler...

Using GCC on Xeon Phi...

How to offload particular thread of a single app to particular Xeon Phi cores?...

Manipulating Masks for doubles on Xeon Phi...

loaddup_pd/unpacklo_pd on Xeon Phi...

Scatter/Gather in Xeon Phi...

xeon phi timer resolution...

Manually control Intel MIC SIMD operations by intrinsics or instructions...

Memory transfer overhead to and from an Intel MIC...