verilog Examples and Free Source Code

Verilog always @(posedge clk) doesn't work...

verilog system-verilog modelsim

Why am I getting parse error in reg declaration?...

compiler-errors verilog system-verilog hdl iverilog

Convert combinational loops into latches...

algorithm verilog

Infinite loop when simulating a Program Counter design with Icarus Verilog...

verilog system-verilog infinite-loop program-counter

Unexpected high impedance state...

verilog system-verilog instantiation

Verilog Icarus giving undefined values...

verilog iverilog risc

SystemVerilog support of icarus (iverilog compiler)...

verilog system-verilog hardware iverilog

Incomprehensible For Loop Icarus Verilog...

verilog system-verilog test-bench iverilog

`$display` output wrong result when caculate `-3*3`?...

verilog vivado

If there are 2 always blocks, which block will be executed first?...

verilog system-verilog hdl

Output *E,TRNULLID: NULL pointer dereference...

verilog system-verilog

How to stay in the same FSM state after input turns zero?...

verilog system-verilog led fsm

Unexpected endcase syntax error in case statement...

verilog system-verilog

$readmemh to load subblocks of memory...

verilog system-verilog

Binary value representation issue in verilog...

verilog quartus

How to swap inout wires within a contained hierarchy (of which is synthesizable)?...

verilog system-verilog

How can I simulate a simple elevator FSM where it can detect overweight?...

verilog system-verilog fsm

Is `x==1'bx` in Verilog?...

verilog

Icarus Verilog crash while compiling dynamic memory module...

crash verilog iverilog

iverilog recursive function causes segmentation fault...

recursion verilog iverilog

`ERROR: [VRFC 10-2063] Module <my_task> not found while processing module instance <'Un...

verilog vivado

How to print array value in VerilogHDL?...

verilog vivado

Why is `-3'd300>5000` true in Verilog?...

verilog vivado

How to print the correct value of a signed reg variable?...

verilog vivado

`ERROR: [VRFC 10-2951] 'xxxx' is not a constant` when use verilog case function...

verilog vivado

How to test if a 3-bit bus has the first bit set on 1 - verilog...

testing verilog bus iverilog

Ring oscillator in Verilog/SystemVerilog - supressing undefined states...

verilog system-verilog iverilog

Icarus Verilog simulation : Scope index expression is not constant: i...

verilog iverilog

`$strobe` and `$display` output different result for the same target...

verilog system-verilog fpga vivado

how can I convince iverilog that the vpi is a system function and not a task...

verilog iverilog